Transistors are key components of modern integrated circuits. To satisfy the requirements of increasingly faster speed, the drive currents of transistors need to be increasingly greater. Since the drive currents of transistors are proportional to gate widths of the transistors, transistors with greater widths are preferred.
The increase in gate widths, however, conflicts with the requirements of reducing the sizes of semiconductor devices. Fin field-effect transistors (FinFET) were thus developed. FIG. 1 illustrates a perspective view of a conventional FinFET. Fin 4 is formed as a vertical silicon fin extending above substrate 2, and is used to form source and drain regions 6 and a channel region therebetween (not shown). A vertical gate 8 intersects the channel region of fin 4. While not shown in FIG. 1, a gate dielectric separates the channel region from vertical gate 8. FIG. 1 also illustrates oxide layer 18, and insulating sidewall spacers 12 and 14 formed on source and drain regions 6 and vertical gate 8, respectively. The ends of fin 4 receive source and drain doping implants that make these portions of fin 4 conductive.
The introduction of FinFETs has the advantageous feature of increasing drive current without the cost of occupying more chip area. However, the FinFETs also suffer from drawbacks. With the increasing down-scaling of FinFETs, the increasingly smaller sizes of the fins result in the increase of the resistances in the source/drain regions, and hence the degradation of device drive currents. The contact resistances between contact plugs and source/drain silicide regions are also increased due to the small fin areas. Additionally, it is difficult to form contact plugs connected to source/drain silicide regions of the FinFETs. This is because the fins of the FinFETs have small areas, the landing areas for the corresponding contact plugs are thus small. The process window for landing contact plugs accurately on fins is thus small.
Accordingly, what is needed in the art is a semiconductor device that may incorporate FinFETs thereof to take advantage of the benefits associated with increased drive currents without increasing the chip area usage while at the same time overcoming the deficiencies of the prior art.